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CXB1575AQ
155Mbps Clock & Data Recovery with High Sensitivity Limiting Amplifier For the availability of this product, please contact the sales office.
Description The CXB1575AQ achieves 3R optical-fiber communication receiver functions (Reshaping and Regenerating and Retiming) on a single chip. This IC also equipped with the signal interruption alarm output, which is used to discriminate the existence of data input. Features * Auto-offset canceler circuit * Signal interruption alarm output * No reference clock required * Single 3.3V power supply Applications * SONET/SDH: 155.52Mbps * ATM: 155.52Mbps Absolute Maximum Ratings * Supply voltage * Storage temperature * Input voltage difference: | VD-VDN | * TTL input voltage * Output current (Continuous) (Surge) Recommended Operating Conditions * Supply voltage * Termination voltage (for RCK/RDATA) * Termination voltage (for SDE) * Termination resistance (for RCK/RDATA) * Termination resistance (for SDE) * Operating temperature 40 pin QFP (Plastic)
VCC - VEE Tstg Vdif VinT IO
-0.3 to +5.0 -65 to +150 0 to 2.5 -0.5 to 5.5 0 to 50 0 to 100
V C V V mA mA
VCC - VEE 3.069 to 3.465 VCC - VT1 1.8 to 2.2 VT2 VEE RT1 46 to 56 RT2 460 to 560 Ta -40 to +85
V V V C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E97Y13-PS
CXB1575AQ
Block Diagram and Pad Configuration
CAP1B
VEEP1
VEEP1
VEEP2
LPFB
LPFA
NC
VCCP
30 29
28
27 26
25
24
23
CAP1
22
21
VEER1
20 VEER2 REXT 31 LKDT 32 VEEG 33 VCO Up phase/ charge frequency pump Down detector 1 Mux. 0 D EXCK 35 CKSEL 36 SQLCH 37 SDC 38 SDE 39 SDEN 40 peak hold peak hold D-FF CK Reset 15 HYS 14 VEER3 13 CAP2 12 CAP3 11 NC 19 DN 18 D
17 VCCR 16 DOWN
VCCG 34
1
2
3
4
5
6
7
8
9
10
RDATAN
RDATA
VEEE1
VEEG
RCK
VCCE1
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VCCE2
VEEE2
RCKN
VCCG
CXB1575AQ
Pin Description Typical pin voltage (V) Pin No. Symbol DC AC 1 VCCE1 3.3 Equivalent circuit Description Positive supply for RDATA/RDATAN output circuits.
VCCE1
2
RDATAN
1.6 to 2.4
2
Retimed data outputs.
3
RDATA
1.6 to 2.4
3
VEEE1
4 5, 33 6, 34 7
VEEE1 VEEG VCCG VEEE2
0 0 3.3 0
VCCE2
Ground for RDATA/RDATAN output circuits. Ground for digital circuits. Positive supply for digital circuits. Ground for RCK/RCKN outputs circuits. 1.6 to 2.4
8
8
RCKN
Recovered clock outputs.
9
RCK
1.6 to 2.4
9
VEEE2
10 11
VCCE2 NC
3.3
Positive supply for RCK/RCKN output circuits. No connect
10p 12 13 VCCR
12
CAP3
2 Connect a peak hold capacitor for signal detector. Typically 470pF.
13
CAP2
2
5A
5A
VEER
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CXB1575AQ
Typical pin voltage (V) Pin No. Symbol DC AC 14 VEER3 0
Equivalent circuit
Description Ground for signal detector.
VCCR
Bias Generator
15
HYS
0.2
15
VEER3 VCCR
Connect to VEER3 through an external resistor to determine signal detect hysteresis width (P). When connect to VEER3 directly; P 6dB (Typ.) When connected 8.2k to VEER3; P 3dB (Typ.)
16
DOWN
3
16
Connect to VCCR through an external resistor to decrease signal detect level (SDL). When open, SDL sets to 18mVp-p. (single-ended)
VEER3
17
VCCR
3.3
Positive supply for signal detector.
18
D
VCCR
Serial data stream inputs. 19 DN
18 19 22 23
22
CAP1
2.2
VEER1 VEER2
23 20 21 24
CAP1B 2.2 VEER2 VEER1 VCCP 0 0 3.3
Connect an external capacitor, which determines low cut-off frequency for DC feedback loop. Typically 0.22F.
Ground for post amplifier. Ground for post amplifier. Both VEER1 and VEER2 must be grounded. Positive supply for PLL circuits.
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CXB1575AQ
Typical pin voltage (V) Pin No. Symbol DC AC
Equivalent circuit
Description
VCCP
25
LPFA
3.1
25 26
Connect an external loop filter capacitor. Typically 0.68F (155.52Mbps).
26
LPFB
3.1
VEEP2 VEEP1
27 28 29, 30
VEEP2 NC VEEP1
0
Ground for PLL circuits. No connect
0
Ground for PLL circuits. Both VEEP1 and VEEP2 must be grounded.
VCCP Bias Generator 31 VEEP2
31
REXT
0.4
Connect to VEEP1 through an external resistor to determine VCO frequency. Typically 1.8k.
VCCG
32
LKDT
0.2 to 3.1
32
Lock detector (TTL). Driven low, while synchronization is lost.
VEEG
VCCG
35
EXCK
1.3
35
External clock input (ECL). For testing only. Normally, left open.
VEEG
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CXB1575AQ
Typical pin voltage (V) Pin No. Symbol DC AC
Equivalent circuit
Description
VCCG
36
CKSEL
3.3
36
Clock selector (TTL). When low, EXCK is active instead of VCO output. Normally, left open.
VEEG
VCCG
37
SQLCH 3.3
37
TTL input. When Low, RCK and RDATA are fixed Low, in case of data loss. When high, RCK outputs VCO free-run frequency, in case of data loss.
VEEG
VCCG
38
SDC
0.2 to 3.1
38
Signal detect output (TTL). Driven low, while input serial data is lost.
VEEG
39
SDE
1.6 to 2.4
VCCG
39
40
SDEN
1.6 to 2.4
40
Signal detect outputs (ECL). SDE is driven low, while input serial data is lost.
VEEG
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CXB1575AQ
Electrical Characteristics * DC characteristics Item Supply current TTL input High voltage TTL input Low voltage RDATA/RCK output High voltage RDATA/RCK output Low voltage SDE output High voltage SDE output Low voltage TTL output High voltage TTL output Low voltage Maximum input voltage amplitude D/DB input resistance 1 Ta = 0C to +85C Symbol ICC VIHT VILT VOH11 VOL11 VOH21 VOL21 VOHT VOLT Vmax Rin 51 to VCC - 2V 51 to VCC - 2V 510 to VEE 510 to VEE IOH = -0.2mA IOL = 2.1mA 1600 2250 3000 3750 (VCC = +3.069 to +3.465V, VEE = GND, Ta = -40C to +85C) Conditions All outputs open 2 0 VCC - 1.1 VCC - 1.88 VCC - 1.1 VCC - 1.88 2.4 0.5 Min. Typ. 70 Max. 100 3.465 0.8 VCC - 0.83 VCC - 1.55 VCC - 0.83 VCC - 1.55 Unit mA V V V V V V V V mV
* AC characteristics Item Post amplifier gain Signal detect hysteresis width Signal detect response assert time1 Symbol GL P Tas
(VCC = +3.069 to +3.465V, VEE = GND, Ta = -40C to +85C) Conditions Min. 50 HYS = VEER3, Rd = 22k 3 0 2.3 with 12kHz high pass filter 0.008 90 0.06 f = 10Hz f = 30Hz 1.5 1.5 1.5 1.5 0.15 16 16 16 4 0.5 UIp-p 130 0.1 8 100 100 Typ. Max. Unit dB dB s s UIrms kHz dB
Signal detect response deassert time1 Tdas Jitter generation2 RJ PLL band width2 FC Jitter peaking2
Jitter tolerance2, 3
f = 300Hz f = 6.5kHz f = 65kHz
PLL capture range2 PLL pull in time2 RCK, RDATA output rise time RCK, RDATA output fall time
DRSEL = High Tp Tr Tf DRSEL = High 51 to VCC - 2V, 20% to 80% 51 to VCC - 2V, 20% to 80%
155.40 155.52 155.60 Mbps 42 600 600 1000 1000 ms ps ps
1 D = 155.52Mbps, PN23-1 pattern, 100mVp-p single-ended, Rd = OPEN, CAP2/3 = 470pF 2 D = 155.52Mbps, PN23-1 pattern, 20mVp-p single-ended, Cp = 0.68F 3 Bit Error Rate Threshold: 1E - 10
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CXB1575AQ
DC Electrical Characteristics Measurement Circuit
0.68F
30 29
28
27 26
25
24
23
0.22F
22 21
1.8k 31 32 33 VCO Up phase/ charge frequency pump Down detector 1 Mux. 0 D 35 36 37 38 510 510 39 40 peak hold peak hold D-FF CK Reset
20 19 18
17 16 15 14 13 12 11 470pF 470pF
34
1
2
3
4
5
6
7
8
9
10
51
51
2V
VEE
Vcc
-8-
2V
3.3V
51
51
CXB1575AQ
AC Electrical Characteristics Measurement Circuit
-1.3V
33F
0.1F
0.68F
0.22F 24 23 22 21
30 29
28
27 26
25
1.8k 31 32 33 VCO phase/ charge frequency pump Down detector 1 Mux. 0 D 35 36 37 510 38 39 40 510 peak hold peak hold D-FF CK Reset Up
20 19 18 0.01F 17 16 15 14 13 470pF 12 470pF 11 0.01F 50 50
0.1F
34
0.1F
1 +2V 0.1F
2
3
4
5
6
7
8
9
10
Z = 50
Z = 50
Z = 50
Z = 50
Data
1M
1M
1M
1M
Clock
50
50
50
Jitter Source Oscilloscope Oscilloscope Bit Error Rate Counter Pulse Pattern Generator
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Clock
Data
Z = 50
CXB1575AQ
Application Circuit
0.68F 30 29 28 27 26 25
0.1F
Analog Supply2
0.22F 23 22 21
24
20 130 0.01F 31 1.8k 32 33 VCO Up phase/ charge frequency pump Down detector 1 Mux. 0 D-FF D CK Reset peak hold peak hold 19 18 0.01F 91 17 16 15 14 470pF 13 470pF 12 11 Analog Supply1 0.1F 91 130
34 35 36 37 38 39 40
1
2
3
4
5
6
7
8
9
10
0.1F
Digital Supply
40H 33F 3.3V 33F
Digital Supply Analog Supply1 Analog Supply2
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
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CXB1575AQ
Notes on Operation 1. Limiting amplifier block The limiting amplifier block is equipped with the auto-offset canceler circuit. When external capacitors C1 and C2 are connected as shown in Fig. 1, the DC bias is set automatically in this block. External capacitor C1 and IC internal resistor R1 determine the low input cut-off frequency f2 as shown in Fig. 2. Similarly, external capacitor C2 and IC internal resistor R2 determine the high cut-off frequency f1 for DC bias feedback. Since peaking characteristics may occur in the low frequency area of the amplifier gain characteristics depending on the f1/f2 combination, set the C1 and C2 so as to avoid the occurrence of peaking characteristics. The target values of R1 and R2 and the typical values of C1 and C2 are as indicated below. When a single-ended input is used, provide AC grounding by connecting Pin 19 to a capacitor which has the same capacitance as capacitor C1. R1 (internal): 3k f2: 5.3kHz C1 (external): 0.01F C2 (external): 0.22F R2 (internal): 10k f1: 7.2kHz
D C1
18 To IC interior 19 C1 R1 R1 R2 C2 22 23 R2
Fig. 1
Feedback frequency response
Amplifier frequency response
Gain
f1
f2 Frequency
Fig. 2
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CXB1575AQ
2. Alarm block This block provides a signal interruption alarm output used for open fibre control (OFC). Signal detect threshold level and hysteresis width are both user adjustable. Signal detect threshold default level is 18mVp-p (single-ended). An external resister Rd between DOWN and VCCR decrease it. Typical characteristics of Rd vs. threshold level is shown in fig. 7, 8. Hysteresis width can be also decreased by an external resister RH. Typical characteristics of RH vs. P is shown in fig. 9. Timing chart of signal detect function is shown in fig. 5. SD response assert/deassert time are decided by peak hold capacitor CR and CS.Their typical value is 470pF for 155Mbps operation.
VDAS Deassert level VAS Assert level High level
SD output
Low level
Rd
Rh
Cs
CR
Cs : 470pF CR : 470pF 12
Small
VDAS
VAS Large 3dB 3dB Alarm setting input level Hysteresis
17
16
15
14
13
Input electrical signal amplitude
Fig. 3
Fig. 4
Data input (D)
Hysteresis width
Alarm setting level
Alarm output (SDEN)
Alarm output (SDE, SDC) Assert time Deassert time
Fig. 5. Timing Chart
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CXB1575AQ
3. Clock and Data recovery block Clock recovery is reallized by fully integrated phase locked loop (PLL), which needs no external reference clock. PLL accepts scrambled NRZ data with 50% mark density. Two external components Re and Cp are required. Their recommended values are shown in fig. 6.
Cp
30
29
27
26
25
31 Re Re :1.8k Cp :0.68F (155.52Mbps)
Fig. 6 Re is a resistor which decides VCO center frequency. To reduce the temperature dependence of the VCO oscillation frequency, Re should have a small temperature coefficient. In addition, Re should place as near as IC terminal to obtain good jitter performance. Cp is a loop filter capacitance. Since loop damping factor is function of Cp, Cp is also important to have a small temperature coefficient. Damping factor is given as 20,000 x Cp (@ = 1/2) 3 Recommended Cp value gives a of 10, and jitter peaking of under 0.1dB is specified.
3 : data transition density
4. Others Pay attention to handling this IC because its electrostatic discharge strength is weak.
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CXB1575AQ
20
20
Assert/Deassert level [mVp-p, single-ended]
15 10 5 0
Assert/Deassert level [mVp-p, single-ended]
15 10 5 0
Vast (mVp-p) Vdast (mVp-p) 1 10 Rd [k] VCC = 3.3V, Ta = 27C D = 155.52Mbps, PRBS23-1 20mVp-p, single-ended Rh = 0 100 1000
Vast (mVp-p) Vdast (mVp-p) 1 10 Rd [k] VCC = 3.3V, Ta = 27C D = 155.52Mbps, PRBS23-1 20mVp-p, single-ended Rh = 8.2k 100 1000
Fig. 7. Rd vs. SD assert/deassert level (Rh = 0)
Fig. 8. Rd vs. SD assert/deassert level (Rh = 8.2k)
20
Assert/Deassert level [mVp-p, single-ended]
15 10 5 Vast (mVp-p) Vdast (mVp-p) 0 0 5 10 15 Rh [k] 20 25
VCC = 3.3V, Ta = 27C D = 155.52Mbps, PRBS23-1 20mVp-p, single-ended Rd =
Fig. 9. Rh vs. SD assert/deassert level (Rd = )
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CXB1575AQ
Example of Representative Characteristics
400mV/div
VCC = 3.3V, Ta = 27C D = 155.52Mbps, PRBS23-1 20mVp-p, single-ended
1.0ns/div
Fig. 10. RCK/RDATA output waveform
5
100 OC-3 Mask
Jitter amplitude [dB]
0 -5 -10 -15 -20 -25 -30 102 103 104 105
Amplitude [UI]
10
1
OC-3 Template
106
107
Modulation frequency [Hz] VCC = 3.3V, Ta = 27C D = 155.52Mbps, PRBS23-1 20mVp-p, single-ended
0.1 102
103
104
105
106
Modulation frequency [Hz] VCC = 3.3V, Ta = 27C D = 155.52Mbps, PRBS23-1 20mVp-p, single-ended Threshold = 1E - 10
Fig. 11. Jitter transfer function
Fig. 12. Jitter tolerance
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CXB1575AQ
Package Outline
Unit: mm
40PIN QFP (PLASTIC)
9.0 0.4 + 0.4 7.0 - 0.1 30 21
+ 0.35 1.5 - 0.15 + 0.1 0.127 - 0.05 0.1
31
20
A
40 1 0.65 + 0.15 0.3 - 0.1 + 0.15 0.1 - 0.1
11
10 0.24 M
0 to 10
0.5 0.2
(8.0)
PACKAGE STRUCTURE
PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER / PALLADIUM PLATING 42/COPPER ALLOY 0.2g
DETAIL A SONY CODE EIAJ CODE JEDEC CODE QFP-40P-L01 QFP040-P-0707
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